1. Field of the Invention
The present invention relates to the formation of high density integrated circuits and, more particularly, to the simplified formation of MOSFET devices having LDD source/drain structures.
2. Description of the Related Art
Very small field effect transistors (FETs), i.e., those FETs made in accordance with small design rules, often form one or both of the FET source/drain regions with a majority carrier concentration that decreases near the channel region of the FET. Because these structures are most frequently provided for the drain regions of FETs, source/drain regions that have a decreased majority carrier concentration adjacent the channel region of the FET arc generally said to have a "lightly doped drain" or "LDD" structure, despite the slight misnomer of applying this label to the source region of the FET. The simplest and most frequently implemented LDD structure is one where the source/drain region has two distinct doping levels, with the lower doping level lying next to the channel of the FET and the relatively higher doping level displaced laterally away from the FET. This structure reduces the electric field between the source/drain regions and between the gate and the source/drain region which has the LDD structure. In essence, the more lightly doped portion of the LDD structure acts as a series resistance between the more highly doped portion of the LDD source/drain region and the channel and, in some cases, the gate of the FET. There is a potential drop across the more lightly doped portion of the LDD source/drain region so that the electric fields corresponding to a potential applied to the source/drain region fall off across the lightly doped portion of the LDD source/drain region. The reduced electric fields adjacent the lightly doped portion of the LDD reduce several FET degradation problems related to the so-called hot carrier effect, including electron injection into the gate oxide layer.
FIGS. 1 and 2 illustrate steps in the most common process used for forming a MOSFET (metal oxide semiconductor FET) with source/drain regions having an LDD structure. Referring to FIG. 1, the illustrated FET is formed on a P-type substrate 10 and include field isolation structures 12 to isolate the FET from other, adjacent FETs or other devices. The illustrated FET is one of what is typically an array including a large number of FETs in typical integrated circuit devices. Shallow trench isolation structures of the type illustrated in FIG. 1 might be formed by etching an array of trenches into the silicon substrate 10 and then filling the trenches with a combination of thermally grown silicon oxide and chemical vapor deposited (CVD) silicon oxide. Other field isolation structures include field oxide regions formed entirely by thermal oxidation, as in the conventional local oxidation of silicon (LOCOS) method. A gate oxide layer 14 is formed by thermal oxidation on the active device region between the field isolation regions 12 and a polysilicon gate electrode 16 is formed on the gate oxide layer 14. Polysilicon gate electrodes 16 are formed by depositing a layer of polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD). The gate electrode may be doped in situ by adding a dopant gas such as phosphine or arsine to the CVD silane source gas, or the gate electrode may be doped by implanting impurities into the polysilicon and activating the impurities to render the polysilicon layer conductive. The gate electrodes are patterned using conventional photolithography techniques. Variations on the illustrated gate electrode structure are known. For example, the layer of polysilicon might be covered by a layer of a refractory metal or by a metal suicide to reduce the resistivity of the gate electrode. A layer of silicon oxide or other insulator might also be provided over the polysilicon gate electrode 16 to protect the electrode in subsequent processing steps and, often, to serve as an etch stop for subsequent etching steps.
The LDD source/drain regions are formed in a two stage implantation process. After the gate electrode 16 has been defined by photolithography, a first, comparatively low level implantation is provided into those portions of the active device regions not masked. The implantation is typically, but not always, made with a dopant of a conductivity type opposite to the conductivity type of the substrate 10 surface region under the gate electrode. This implantation forms lightly doped regions 18 self-aligned to the edges of the gate electrode 16 and extending from below the edges of the gate electrode 16 to the field isolation structures 12 on either side of the gate electrode 16. Next, as shown in FIG. 2, sidewall oxide spacer structures 20 are formed adjacent the gate electrode 16 by first depositing CVD silicon oxide over the device and then anisotropically etching back the oxide layer to expose the substrate over the existing lightly doped portions 18 of the source/drain regions. Etching back the CVD oxide layer produces the spacer oxide regions 20 on either side of the polysilicon gate electrodes 16. After the spacer oxide regions 20 are provided on either side of the polysilicon gate electrodes 16, a second, heavier ion implantation is made self-aligned to the spacer oxide regions 20 with a dopant of a conductivity type opposite to the conductivity type of the substrate under the gate electrode 16.
The silicon oxide spacers of this first strategy for forming LDD source/drain structures are typically left in place in the completed device. Thus, the spacers are present in all future processing steps. Because the oxide spacer structure is made of a material different from the gate electrode and the substrate, subsequent thermal processing introduces stress between the spacers and the gate electrode and substrate. These stresses can introduce defects or otherwise adversely effect the properties of the source/drain regions or the FET.
An alternative strategy for forming LDD source/drain regions is illustrated in FIGS. 3-4. In this variation of the process for forming LDD source/drain regions adjacent the gate of a FET, the more heavily doped portions of the LDD source/drain regions are formed first and then the more lightly doped portions of the LDD source/drain regions are formed. In this alternative method, temporary spacer structures are used in the initial implantation step to space the more heavily doped portions of the source/drain regions away from the gate electrode. The spacer structures are then removed, and the more lightly doped portions of the source/drain regions are formed. An intermediate stage in the manufacture of a MOSFET device according to this alternative strategy is shown in FIG. 3, where a polysilicon gate electrode 16 is formed on a gate oxide layer 14 to cover the active device region between field isolation structures 12. The gate electrode 16 is covered by a layer of silicon oxide (silicon oxide coating 26) by either CVD or by thermal oxidation of the polysilicon gate electrode. A layer of polysilicon is then deposited over the device and etched back to form temporary polysilicon spacers 28 spaced from and parallel to the edges of the gate electrode 16. The silicon oxide coating 26 over the gate electrode and the gate oxide layer 14 over the substrate are used as an etch stop for the etching of the polysilicon spacers 28. A first implantation is made into the FIG. 3 structure self-aligned to the polysilicon spacers. This first implantation is a comparatively heavy implantation and forms the more heavily doped portions 30 of the LDD source/drain regions. The polysilicon spacers 28 are then removed, and a second, comparatively light ion implantation is made self aligned to the silicon oxide coating 26 to define the LDD source/drain regions 32.
Both of the LDD source/drain manufacturing processes described in the background require formation of a spacer and require two distinct implantation steps separated by a number of processing steps. Each manufacturing step used in the manufacture of an integrated circuit device carries a cost associated with the longer manufacturing process.